Integrated circuits are manufactured in the form of wafers, each including a plurality of identical chips. After the integrated circuits are formed, the chips are separated, for example, through die-sawing and are packaged. In order to identify wafers, wafer identification (ID) numbers need to be marked on the wafers.
The wafer ID marking can be divided into two categories. Conventionally, wafer IDs are marked on wafers before metal layers are formed. Typically, an oxide layer is formed on a bare wafer and wafer IDs are marked on the oxide layer by using laser to melt the portion of the oxide layer where wafer IDs are to be shown. This type of marking is referred to as front-end-of-line (FEOL) marking. With more and more metal layers and corresponding dielectric layers formed on wafers, however, the wafer marking is now made to surface dielectric layers overlying the metal layers. This type of marking is referred to as back-end-of-line (BEOL) marking.
It has been noted, however, that in BEOL marking, some wafers suffer from unclear wafer IDs. It has also been noted that whether the wafer IDs are clear or not is related to the conditions of the surface layers on which wafer IDs are to be marked. For example, when making laser marks on a combined dielectric layer, including an undoped silicate glass (USG) layer (with a thickness of 12 kÅ), and a silicon nitride (SiN) layer (with a thickness of 7 kÅ), the wafer IDs were not clear. However, when making wafer IDs on an USG layer with a thickness of 6 kÅ, and a SiN layer with a thickness of 4 kÅ, the wafer IDs were clear.
Conventionally, the wafers with unclear wafer IDs need to be marked again manually. However, mis-operation may occur, resulting in the damage of wafers. In addition, the manual wafer ID marking results in the increase of cycle time for delivering end products to clients. New methods for solving the above-discussed problems are thus needed.